The present invention relates to methods and apparatus for forming a gate structure and, more particularly, to methods and apparatus for forming a gate structure of a memory device.
Semiconductor memory devices may be classified as volatile memory devices, such as a dynamic random access memory (DRAM) and static random access memories (SRAMs), which generally lose data with the passage of time, and non-volatile memory devices, such as a flash memory, that generally continuously retain data regardless of the passage of time. The data typically may be rapidly input/output into/from a volatile memory device. On the other hand, the data may be more slowly input/output into/from a non-volatile memory device.
A non-volatile memory device may have a very large memory capacity. A memory cell of the non-volatile memory device may have a vertically stacked gate structure that includes a floating gate formed on a silicon substrate. A multi-layered gate structure may include a first dielectric layer, a floating gate, a second dielectric layer and a control gate. The memory cell may be programmed by moving hot channel electrons from a drain region to accumulate the electrons in the floating gate, thereby increasing a threshold voltage of a cell transistor. The memory cell may be erased by generating a high voltage between the substrate and the floating gate to discharge electrons in the floating gate, thereby decreasing the threshold voltage of the cell transistor.
The first dielectric layer may be referred to as a tunnel oxide layer. The floating gate may serve as a tunneling source in programming and erasing data. The floating gate may include doped polysilicon. The second dielectric layer generally preserves the data in the floating gate. The second dielectric layer may include an oxide/nitride/oxide (ONO) structure. The voltage is typically applied to the control gate to migrate the electrons in the substrate to the floating gate when programming the data or the electrons in the floating gate to the substrate when erasing the data. To reduce a resistance of the control gate, the control gate may include a polysilicon layer and a metal layer, such as a tungsten layer, formed on the polysilicon layer.
In a conventional method of forming a non-volatile memory device that includes the above-mentioned structure, the first dielectric layer is formed on the semiconductor substrate. The doped polysilicon layer is formed on the first dielectric layer. The second dielectric layer having the ONO structure is formed on the doped polysilicon layer. A polysilicon layer and a tungsten layer are sequentially formed on the second dielectric layer. The tungsten layer, the polysilicon layer, the second dielectric layer, the doped polysilicon layer and the first dielectric layer are patterned to form a gate pattern including a tungsten layer pattern, a polysilicon layer pattern, a second dielectric layer pattern, a doped polysilicon layer pattern and a first dielectric layer pattern. The tungsten layer pattern and the polysilicon layer pattern correspond to the control gate discussed above and the doped polysilicon layer pattern corresponds to the floating gate.
A spacer is typically formed on a sidewall of the gate pattern. As nitride has a high dielectric constant, a spacer including nitride may function as a parasitic capacitor. To limit or prevent the spacer from functioning as a parasitic capacitor, an oxide spacer having a dielectric constant lower than that of nitride may be formed on the sidewall of the gate pattern. A nitride spacer may then be formed on the oxide spacer.
However, when the oxide spacer is formed, tungsten may be reacted with oxygen so that whiskers grow from the tungsten layer pattern. The whiskers may interfere with electromigration during operation of the control gate. Therefore, in a process for forming a non-volatile memory device that has the control gate including tungsten, a process for preventing oxidation of the tungsten layer is generally carried out before forming the oxide spacer.
To prevent the oxidation of the tungsten layer, according to a conventional method, a nitrogen gas may be applied to the semiconductor substrate to form an oxidation-preventing layer on an outer wall of the tungsten layer, before the oxide spacer is formed. Also, as preventing the oxidation of the tungsten layer in applying the nitrogen gas to the semiconductor substrate may be required, a chamber in which the semiconductor substrate is positioned is typically maintained under an atmosphere free from oxygen.
However, the process for preventing the oxidation of the tungsten layer is typically performed on only one semiconductor substrate, not on a plurality of semiconductor substrates. As a batch type chamber generally has a large inner space into which semiconductor substrates are loaded, it may be difficult to form the atmosphere free from oxygen in the inner space of the batch type chamber. In particular, although a batch type chamber is typically exhausted using vacuum, oxygen may partially remain in the batch type chamber. As a result, the whiskers may partially grow from the tungsten layer when applying the nitrogen gas to the semiconductor substrate.
According to a conventional method, one semiconductor substrate is loaded into a single-substrate type chamber having a very small inner space compared to a batch chamber. The oxidation-preventing layer is then formed on the outer wall of the tungsten layer. Thus, the conventional method may be carried out on the semiconductor substrates one by one, in which case the time for forming the oxidation-preventing layer on the tungsten layer of all of the semiconductor substrates is generally lengthened. As a result, the conventional method may cause a decrease of yield for manufacturing the non-volatile memory device.
It is typically not necessary to perform the process for forming the oxide spacer on the gate structure having the oxidation-preventing layer on the semiconductor substrates one substrate at a time. Therefore, the semiconductor substrates are typically loaded into a deposition chamber. The process for forming the oxide spacer is collectively carried out on the batch of semiconductor substrates in the deposition chamber. That is, the process for forming the oxidation-preventing layer and the process for forming the oxide spacer are generally separately performed in two different chambers, which may render the conventional method very complicated.
In addition, the substrate having the oxide spacer is generally transferred to another deposition chamber in which the process for forming the nitride spacer is carried out. As a result, to form the gate structure of the non-volatile memory device in accordance with such a conventional method, the chamber for forming the oxidation-preventing layer, the chamber for forming the oxide spacer and the chamber for forming the nitride layer are typically required to be separate chambers.